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Espressif Systems /ESP32-C2 /LEDC /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OVF_INT_ST)OVF_INT_ST 0 (TIMER1_OVF_INT_ST)TIMER1_OVF_INT_ST 0 (TIMER2_OVF_INT_ST)TIMER2_OVF_INT_ST 0 (TIMER3_OVF_INT_ST)TIMER3_OVF_INT_ST 0 (DUTY_CHNG_END_CH0_INT_ST)DUTY_CHNG_END_CH0_INT_ST 0 (DUTY_CHNG_END_CH1_INT_ST)DUTY_CHNG_END_CH1_INT_ST 0 (DUTY_CHNG_END_CH2_INT_ST)DUTY_CHNG_END_CH2_INT_ST 0 (DUTY_CHNG_END_CH3_INT_ST)DUTY_CHNG_END_CH3_INT_ST 0 (DUTY_CHNG_END_CH4_INT_ST)DUTY_CHNG_END_CH4_INT_ST 0 (DUTY_CHNG_END_CH5_INT_ST)DUTY_CHNG_END_CH5_INT_ST 0 (OVF_CNT_CH0_INT_ST)OVF_CNT_CH0_INT_ST 0 (OVF_CNT_CH1_INT_ST)OVF_CNT_CH1_INT_ST 0 (OVF_CNT_CH2_INT_ST)OVF_CNT_CH2_INT_ST 0 (OVF_CNT_CH3_INT_ST)OVF_CNT_CH3_INT_ST 0 (OVF_CNT_CH4_INT_ST)OVF_CNT_CH4_INT_ST 0 (OVF_CNT_CH5_INT_ST)OVF_CNT_CH5_INT_ST

Description

Masked interrupt status

Fields

OVF_INT_ST

This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.
TIMER1_OVF_INT_ST

This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.
TIMER2_OVF_INT_ST

This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.
TIMER3_OVF_INT_ST

This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.
DUTY_CHNG_END_CH0_INT_ST

This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1.
DUTY_CHNG_END_CH1_INT_ST

This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1.
DUTY_CHNG_END_CH2_INT_ST

This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1.
DUTY_CHNG_END_CH3_INT_ST

This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1.
DUTY_CHNG_END_CH4_INT_ST

This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1.
DUTY_CHNG_END_CH5_INT_ST

This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1.
OVF_CNT_CH0_INT_ST

This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
OVF_CNT_CH1_INT_ST

This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
OVF_CNT_CH2_INT_ST

This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
OVF_CNT_CH3_INT_ST

This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
OVF_CNT_CH4_INT_ST

This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
OVF_CNT_CH5_INT_ST

This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data